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Freescale’s multi-core platform surpasses Moore’s Law
By combining Power architecture, scalable interconnect and 45nm technology, Freescale has set a new milestone in multi-core embedded systems. This is the Multi-core Communications Platform, unveiled yesterday, which, in the words of the official press release, provides “a breakthrough in efficiency, performance and size.”. Significant benefits of new Freescale approach – reduced power consumption and increased integration – driven by the move to 45nm process technology.
The need for a brand new platform that meets the increased requirements for performance and bandwidth is growing as the popularity of new network services among home and corporate users. According to Freescale, the step-by-step, gradual implementation of innovative solutions is no longer sufficient for the element base to keep up with the progress taking place at a higher level of abstraction. There is a need for a radical revision and renewal of the paradigm underlying communication platforms. After analyzing possible alternatives, the company relied on multi-core and the transition to more subtle technical process standards. Due to this, it is argued, it was possible to lay in the new product the potential sufficient to ensure an acceptable lifetime of solutions built on its basis
The heart of the new platform is CoreNet technology, a highly scalable single-chip interconnect. Its development focused on eliminating bus contention, bottlenecks and latency associated with shared bus and shared memory architecture found in most multi-core platforms. CoreNet technology works with a large number of cores (more than 32) and in heterogeneous configurations.
In turn, the transition to a 45nm process technology helped to significantly improve performance, integration and energy efficiency of products – according to Freescale, the performance of the new platform exceeds those predicted by Moore’s Law. In particular, the 45nm blocks used by Freescale engineers allowed the creation of a multilevel hierarchy of coherent cache access mechanisms, in which each core can have its own L2 cache and access to a shared L3 cache of several megabytes. The maximum clock speed of the e500-mc core based on the e500 core will be 1.5 GHz.
In the future, Freescale will present a roadmap for products built on the new platform. Trial samples of the first products should appear at the end of next year.
Source: Freescale Semiconductor