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Altera begins shipping 65nm FPGA Stratix III
Altera, which announced in June that it will ship EP3C120, the new flagship of the 65nm series of 65nm budget Cyclone III FPGAs, has begun shipping the EP3SL150, the first member of another 65nm FPGA family, the Stratix III. The matrix includes 150 thousand. logical elements. The novelty has a very low power consumption – according to the manufacturer, the minimum among FPGAs of such density and speed. EP3SL150 chip is designed for a wide range of applications, such as high-performance computers, base stations of new generation cellular networks, network infrastructure equipment, imaging solutions.
Stratix III appliances consume 45% less energy and 25% outperform competitors’ offerings, according to the company. What’s more, when combined with the Altera Quartus II design toolkit, these FPGAs enable functionality not available from other vendors, such as fully compliant with the recently approved JEDEC DDR3 SDRAM interface support.
To reduce the power consumption of the Stratix III while maintaining high performance, the developers applied a set of measures called Programmable Power Technology. Behind this name is power management technology that allows each programmable logic block, DSP, and memory block to operate independently in “high speed” or “low power” mode, depending on the needs of the application. In addition, the unique Selectable Core Voltage feature allows you to select the core voltage from two values: 1.1 V for high-performance applications or 0.9 V for applications where lower power consumption is a priority.